A phase lock loop (PLL) is an electronic system that locks in phase and frequency of an output signal to the phase and frequency of an input signal. A PLL is widely employed in applications in communication systems, such as FM demodulators, stereo demodulators, tone detectors, and frequency synthesizers. A PLL is also commonly employed in digital applications that require a high-frequency periodic signal to synchronize the events between high-performance digital circuits. A PLL is particularly desirable to be implemented by advanced very-large-scale-integrated-circuit (VLSI) manufacturing technologies, and integrated with semiconductor integrated circuits (IC) for the various applications fields.
FIG. 1A is a system diagram illustrating the building blocks of an existing PLL, which generally is a nonlinear feedback circuit. The input signal Fin is typically a periodic clock signal generated off chip from a reference clock source, such as a crystal oscillator. Fin is compared with a local clock signal Flocal, which is typically a divided version of the output signal Fout. The phase detector determines the relative phase difference between the two signals and outputs a signal that is proportional to this phase difference. The output signal from the phase detector is subsequently fed into a charge pump that converts the signal into an analog voltage Vc. This analog voltage is typically used as the VCO control signal. When there is a phase difference between the input signal Fin and the local signal Flocal, the value of this analog voltage may increase or decrease to speed up or slow down the VCO, which causes the local signal Flocal to catch up with the input signal Fin or to eliminate the lead of the local signal Flocal. When an automatic follow-up between the input signal Fin and the local signal Flocal is achieved, the output signal Fout is said to be locked on the input signal Fin. This behavior makes PLLs particularly useful in applications where an input signal contains desired information, whereas its frequency varies in time. In practice, the analog voltage Vc generated by the charge pump first passes a loop filter, typically a low-pass filter, where the high-frequency components are removed from the VCO control signal. The dc component of Vc is then fed into the VCO in order to reduce undesirable jitter in the output signal Fout.
FIG. 1B is a graph of an output frequency vs. control voltage of the VCO illustrated in FIG. 1A. The linear relationship between the frequency of the output signal Fout and the magnitude of the VCO control signal Vc may be expressed as the following equation:Fout=Kvco·Vc  (1)where Kvco represents the slope of the linear output frequency vs. control voltage relationship, and is the constant VCO frequency gain. Fout is the frequency change in the output signal in response to a VCO control signal Vc. As an example, a VCO in a PLL fabricated through a 0.25 μm processing technology has a constant frequency gain of about 0.25 MHz/mV, where one millivolt swing in the VCO control voltage translates into a quarter of one MHz frequency shift in the output signal Fout.
There are applications where a VCO with fine tuning precision of output frequency is desirable. A PLL having a VCO frequency gain such as that described above provides too coarse a tuning precision to meet the requirements of these applications. Thus, a PLL have a significantly reduced VCO frequency gain is also desirable.